The invention relates to a method and a configuration for operating a multistage counter in one counting direction.
In many technical applications it is necessary to count events. These events can be the frequency of use of an appliance, the passing of persons or vehicles or objects, and the registration of telephone metering pulses or telephone counting cycles. Such events can also be related to the registration of a vehicle usage, for example in an odometer in an automobile or in an operating hours counter in any appliance. Further, the work hours or attendance time of an employee at his or her workplace may be measured. All these cases are characterized by the fact that they are registered with the highest possible accuracy, that is to say as a rule a high value range of counter readings is covered. In addition, in the aforementioned cases it is generally desired that the counter result is not open to manipulation, that is to say it cannot be reset. Such a requirement may be met reliably by a single-stage counter which can count only upward or downward from its previous counter reading. This may be implemented simply, for example through the use of an EEPROM. It is then necessary to have one EEPROM cell for each counter reading, and the EEPROM must be either only writable or only erasable, depending on whether an upward or downward counting is provided.
The first requirement, namely that the greatest possible value range is to be registered by the counter, then leads to the result that, in the case of such an implementation, an EEPROM memory with an appropriate number of storage cells has to be provided. Expressed in numerical terms, this means that, for example in order to achieve a maximum counter reading of 255, exactly 255 counter cells are needed. However, it is nowadays usual to construct configurations of this type to be as small as possible. The use of a multistage counter with 8 bits, that is to say 8 counter cells, likewise leads to a maximum counter reading of 255. A multistage counter of this type (8-bit binary counter) has the drawback, however, that when there is a change in the next counter digit, the preceding counter digit is reset. This means that a multistage counter which counts only in one direction and at the same time is not open to manipulation can be realized only with great difficulty.
European Patent No. EP 0 321 727 describes a circuit configuration in which a number of EEPROM cells are provided in a row. In this case, a number of rows are in turn connected together. The storage cells of one row in each case constitute a uniform value level. It is possible for the stored contents of one row to be erased by a logical monitoring device only when an overflow into the next higher row has taken place. This conventional configuration exhibits precisely the drawbacks explained above, namely it is open to manipulation, in that unidirectional counting is not ensured with certainty since the logic circuit may be manipulated. A similar but somewhat more complicated configuration is explained in European Patent No. EP 0 618 591. An auxiliary storage cell is provided for rewriting each next higher row. The auxiliary storage cell can be programmed and also erased again. Thus this configuration can also be manipulated easily, since the auxiliary storage cells can be both written and erased.
Japanese Patent Document JP 02 090726 A describes a configuration for measuring a periodic signal, using two counters. The periodic signal is fed to both of the counters, in each case via a respective gate. It can be assumed that the counters are not configured such that they count in only one direction, but can at least be reset, since the configuration is a measuring configuration. The respective opening time of the two counters is different by 1/N. The counter result of one of the counters is indicated by a flashing light until the ratio between the two counter results is likewise 1/N. The result of the one of the counters is then indicated continuously. Consequently, the counter results from the two counters do not depend on each other but on the frequency of the periodic signal and the ratio of the opening times of the two gates.
It is accordingly an object of the invention to provide a method and a circuit configuration for operating a multistage counter which overcome the above-mentioned disadvantages of the heretofore-known methods and circuit configurations of this general type and which have an increased security against manipulation.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method of operating a multistage counter in only one counting direction, the method includes the steps of:
changing a counter reading of a single-stage auxiliary counter at given counter readings of a multistage counter, the single-stage auxiliary counter and the multistage counter being changeable in only one counting direction;
registering respective counter readings of the multistage counter and of the single-stage auxiliary counter;
comparing values of the respective counter readings of the single-stage auxiliary counter and of the multistage counter with one another; and
generating an indicator signal based on a comparison result determined in the comparing step.
According to another mode of the invention, the indicator signal indicates a validity of a counter reading of the multistage counter, if the counter reading of the multistage counter is in a given relationship or is consistent with a corresponding counter reading of the single-stage auxiliary counter.
With the objects of the invention in view there is also provided, a counter configuration, including:
a multistage counter configured as a multistage upward counter or as a multistage downward counter;
the multistage counter having at least a given stage and a succeeding stage following the given stage, a counter reading of the given stage being reset to an initial value when a counter reading of the succeeding stage is changed;
a single-stage auxiliary counter configured as a single-stage upward counter or as a single-stage downward counter, the single-stage auxiliary counter being changed when the multistage counter has specific counter readings; and
a comparison device connected to the multistage counter and to the single-stage auxiliary counter, the comparison device performing a comparison between counter readings of the multistage counter and of the single-stage auxiliary counter, and the comparison device supplying an indicator signal corresponding to the comparison.
Due to the simultaneous operation of a single-stage counter which counts only either upward or downward, in addition to the multistage counter, which counts the actual event, and due to the comparison, it is ensured that the counter reading of the multistage counter agrees with the counter reading of the single-stage counter, at least in its order of magnitude. The possibility of manipulation is therefore eliminated with simple measures. If an agreement or correspondence, with a predefined relationship or ratio between the two counters, is not provided, then the indicator signal indicates the lack of validity or reliability. A check is made to see whether the counter reading of the single-stage counter is in a predetermined relationship with the counter reading of the multistage counter. A validity or reliability is provided when the counter readings agree.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method and a configuration for operating a multistage counter in one counting direction, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.